Design of low-power clock generator synchronized with AC power for adiabatic dynamic CMOS logic
نویسندگان
چکیده
منابع مشابه
Design of low-power clock generator synchronized with AC power for adiabatic dynamic CMOS logic
To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the adiabatic dynamic CMOS logic (ADCL), the clock signal of logic circuits should be synchronized with the AC power source. In this paper, the low-power clock generator synchronized with the AC power signal is proposed for ADCL system. From the simulation result, sum...
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2013
ISSN: 1349-2543
DOI: 10.1587/elex.10.20130716